Many types of integrated circuit devices include non-volatile memory cells in order to increase the performance of the integrated circuits. To minimize the additional chip area required for the non-volatile memory cells, cell designers strive for designs which are compact and be reduced in size to match the dimensions of other circuit components within the integrated circuit device. Additionally, non-volatile memory cell designers seek to design non-volatile memory cells that are capable of operating at low power. By developing non-volatile memory cells capable of being programmed and erased at low power, the memory cells become more compatible with existing circuitry in electrically-erasable-programmable-read-only-memory (EEPROM) integrated circuit devices. For example, EEPROM cells typically require 13 to 15 volts for programming and erasing. This voltage level is considerably greater than the 1.8 to 3 volt operating potentials used by many integrated circuits.
Conventional programming and erasing of EEPROM devices is carried out by either hot carrier injection, or by Fowler-Nordheim tunneling. Both conventional programming and erasing methods require application of relatively high voltages to store and remove charge form the floating-gate transistor within the EEPROM cell. Reduced programming voltages can be obtained through the use of a Zener diode within the substrate immediately below the floating-gate electrode. Programming and erasing of an EEPROM cell having a Zener/avalanche diode can be carried out at voltage levels of about 6 to 8 volts. Accordingly, by incorporating an EEPROM device having a Zener/avalanche diode the EEPROM cell can be operated at low power and can be powered by a relatively small power supply.
Typically, an EEPROM cell having a Zener/avalanche diode comprises a source and drain region underlying a floating gate electrode. An implant region is included within the channel of opposite conductivity type to that of the source and drain. This creates a P-N junction in close proximity to the floating-gate electrode.
To program the Zener EEPROM cell, the P-N junction is reversed-biased to create an electric field of approximately 10.sup.6 volt/cm. The electric field generates energetic hot electrons that are injected across the dielectric layer separating the floating-gate from the channel region. A low junction break down voltage can be used for programming by optimizing the P-N junction depth and junction profile.
While the incorporation of Zener/avalanche structures in EEPROM memory cells has reduced the programming and erasing voltage levels necessary for cell operation, further improvements are necessary to fully realize the operational efficiency possible with this type of non-volatile memory cell. Improvements in the structure of individual cells will result in lower power devices that can be programmed and erased at relatively low voltage levels. Further development of EEPROM cells that incorporate sense transistors as part of the read path are needed to provide non-volatile memory cells capable of operation at very low power levels.